Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement
نویسندگان
چکیده
منابع مشابه
High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications
An all-digital on-chip delay measurement (OCDM) architecture with high delay measurement resolution and low supply voltage sensitivity for efficiently detection and diagnosis in the high performance system-on-chip (SoC) applications is presented. Based on the proposed differential delay line pair (DDLP) and an cascadestage delay line, the quantization resolution of the proposed OCDM not only ha...
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The importance of on-chip power-rail inductance in generating delta-I power-supply noise is examined in this paper using systematic circuit simulation of the complete integratedcircuit power net. This source of noise is compared to the resistive IR drop in the net, and to the delta-I noise due to both high-inductanceand low-inductance-bonding packages. Results are presented for a typical on-chi...
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An all-digital on-chip delay sensor (OCDS) circuit with high delay-measurement resolution and low supply-voltage sensitivity for efficient detection and diagnosis in high-performance electronic system applications is presented. Based on the proposed delay measurement scheme, the quantization resolution of the proposed OCDS can be reduced to several picoseconds. Additionally, the proposed cascad...
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ژورنال
عنوان ژورنال: IEEE Transactions on Circuits and Systems II: Express Briefs
سال: 2007
ISSN: 1057-7130
DOI: 10.1109/tcsii.2007.901574